UPD98410S2-K6

Product Details

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ATM QUAD SONET FRAMER

**The µPD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the

functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer, and a reception function to separate the overhead and ATM cell from the data string received from the PMD device and transmit the ATM cell to the ATM layer. The µPD98411 NEASCOT-P40 combines these transmission /reception functions into a port function that is realized as a single 4-port LSI chip. This LSI is ideally suited for use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.**

In addition, the µPD98411 also has a clock recovery function for each port to extract synchronous clock for reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.

FEATURES

• Incorporates an ATM user network interface TC sublayer function for four channels.
• Conforms to ATM FORUM UNI v3.1.
• Incorporates four clock recovery PLLs and one clock synthesizer PLL.
• Conforms to ATM FORUM UTOPIA Level 2 v1.0.
• ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.
• A management interface can be set to either of two modes.
• The line-side PMD interface accepts a P-ECL level input.
• Supports a loopback function.
• Supports a pseudo error generation frame transmission function.
• Incorporates one general input port per channel and three output ports (each able to drive an LED) per channel.
• Supports JTAG boundary scan test (IEEE 1149.1).
• Incorporates a wide range of operation, administration, and maintenance (OAM) functions.
• 0.35-µm CMOS process
• Low power consumption; +3.3 V single-voltage power supply