W89C982AF

GENERAL DESCRIPTION

The Integrated Multiple Port Repeater II (IMPR II) implements the repeater functions specified by section 9 of the IEEE 802.3 standard and twisted pair line transceiver functions conforming to the 10BASE-T standard. The IMPR II provides eight Twisted Pair (TP) Line Transceiver Ports and an Attachment Unit Interface (AUI) port. Each Twisted Pair (TP) Line Transceiver Port can connect to an Ethernet segment through a twisted pair line. The AUI port can connect to a thick Ethernet segment by means of a 50-meter AUI cable. The IMPR II provides an AUI/TP port status direct report function, which uses the ten port status pins and two select pins to indicate collisions, port link/activity, partition, polarity, and network utilization. The inter-IMPR II interface includes signals for connecting more than one IMPR II to increase the total number of hub ports. The manageable functions of the repeater and twisted pair line transceiver in the IMPR II can be accessed through a serial interface.

FEATURES

• Functions conform to IEEE 802.3 section 9 specifications
• Single 5V power supply
• CMOS process for lower power dissipation
• Twisted-Pair (TP) line media interface compatible with 10 BASE-T specifications
• Differential interface compatible with AUI specifications
• Port status direct report function
• Asynchronous Inter-IMPR II interface for large hub applications
• Serial management interface allows for network management and makes port status information accessible
• AUI and TP port carrier sense signals observable through a port activity monitor port
• Internal main state machine performs fragment extension, packet repetition, and collision handling functions
• Internal jabber lockup protection state machine monitors the length of each input packet to prevent transmission of excessively large packets
• Separate partition state machine for each TP port and AUI port can isolate ports when an excessive number of collisions occur and reconnect them using certain algorithms
• On-chip PLL, Manchester encoder/decoder, and FIFO