MC100LVEP210FAG

The MC100LVEP210 is a low skew 1:5 dual differential driver designed with clock distribution in mind. If the VBB output is used, the ECL/PECL input signal can be differential or single-ended. The signals are fan-out to 5 identical differential outputs. The HSTL input can be used when the EP210 is operating in PECL mode. LVEP210 can specifically guarantee low output-to-output skew. Optimized design, layout, and processing minimize intra- and inter-device skew. To ensure strict skew specifications are met, both ends of the differential output need to be equally terminated to 50 Ω even if only one output is used. if no output pair is used, both outputs can be left open (unterminated) without affecting skew. As with most other ECL devices, the MC100LVEP210 can be powered from a positive VCC supply in PECL mode. Therefore, using the LVEP210 in a +3.3 V or +2.5 V system allows for high performance clock distribution. Single-ended CLK input operation is limited to VCC ≤ 3.0 V in PECL mode, or VEE ≤ -3.0 V in NECL mode. designers can take advantage of the LVEP210's performance to distribute low skew clocks on the backplane or motherboard. In a PECL environment, serial or Davyin line terminations are typically used because they do not require additional power. For more information on using PECL, designers should refer to Application Note AN1406/D.