Z85C3010PEG

General Description

The Z80C30/Z85C30 Serial Communications Controller (SCC), is a pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. It is a dual channel, multiprotocol data communications peripheral that easily interfaces with CPU’s with either multiplexed or nonmultiplexed address/data buses.
The advanced CMOS process offers lower power consumption, higher performance, and superior noise immunity. The programming flexibility of the internal registers allow the SCC to be configured to various serial communications applications.

Overview

The features of Zilog’s Z80C30 and Z85C30 devices include:
• Z85C30: optimized for nonmultiplexed bus microprocessors
• Z80C30: optimized for multiplexed bus microprocessors
• Pin-compatible to NMOS versions
• Two independent 0 to 4.1 Mbps, full-duplex channels, each with separate crystal oscillator, Baud Rate Generator (BRG), and Digital Phase-Locked Loop (DPLL) for clock recovery
• Multiprotocol operation under program control; programmable for NRZ, NRZI or FM data encoding
• Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop Bits Per Character, Programmable Clock Factor, Break Detection and Generation; Parity, Overrun, and Framing Error Detection
• Synchronous Mode with Internal or External Character Synchronization on One or Two Synchronous Characters and CRC Generation and Checking with CRC-16 or CRC-CCITT Preset to either 1s or 0s
• SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC Generation and Checking, and SDLC Loop
• Software Interrupt Acknowledge Feature (not available with NMOS)
• Local Loopback and Auto Echo Modes
• Supports T1 Digital Trunk2
• Enhanced DMA Support (not available with NMOS) 10 x 19-Bit Status FIFO 14-Bit Byte Counter
• Speeds
– Z85C3O: 8.5, 10, 16.384 MHz
– Z80C3O: 8, 10 MHz