ADSP-2187NBSTZ-320

GENERAL DESCRIPTION

The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members
appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision.

PERFORMANCE FEATURES

12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sustained performance
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every instruction cycle
Multifunction instructions
Power-down mode featuring low CMOS standby power dissipation with 200 CLKIN cycle recovery from power-down condition
Low power dissipation in idle mode

INTEGRATION FEATURES

ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions
Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM
Dual-purpose program memoryfor both instruction and data storage
Independent ALU, multiplier/accumulator, and barrel shifter computational units
Two independent data address generators
Powerful program sequencer provides zero overhead looping conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA

SYSTEM INTERFACE FEATURES

Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation All inputs tolerate up to 3.6 V regardless of mode
16-bit internal DMA port for high-speed access to on-chip memory (mode selectable)
4M-byte memory interface for storage of data tables and program overlays (mode selectable)
8-bit DMA to byte memory for transparent program and data memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory space permits “glueless” system design
Programmable wait state generation
Two double-buffered serial ports with companding hardware and automatic data buffering
Automatic booting of on-chip program memory from byte wide external memory, for example, EPROM, or through internal DMA Port
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final systems